First-in, first-out (FIFO) memory is used in buffering applications between devices operating at different clock speeds or in flow control applications where data is stored temporarily for further processing. When using FIFO memory, the first data written to the memory is the first data released. In this fashion, FIFO memory achieves its buffering and flow control functions. A common use of FIFO memory is between two communication busses either clocked at different frequencies or having asynchronous clocks. FIFO memory is also common in inter-processor communication, where two processors are clocked at different frequencies.
Many types of FIFO memory chips are commercially available and in use in the computing industry. Chips vary in their density, capacity, supply voltage, operating temperature and interface details, among many other properties. FIFO memory can be implemented in a variety of memory types, including: random access memory (RAM), which includes dynamic RAM (DRAM), static RAM (SRAM) and many other variations, flip-flops, latches or any other suitable form of storage. One significant distinction among FIFO memory implementations is whether an implementation communicates synchronously or asynchronously. In synchronous FIFO memory, read and write cycles use the same clock for their operations. Synchronous FIFO memory is well suited for high-performance systems, clocked at high speeds. In asynchronous FIFO memory, read and write cycles use different clocks, which introduces metastability issues. Metastable events are when a logic device is neither at logic high or logic low, but at an indeterminate level. This leads to data errors. To mitigate the risk of metastability in asynchronous FIFO memory, designers typically take steps to synchronize read and write clocks, or synchronize read and write pointers to the read and write clocks.